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LTC3806 Synchronous Flyback DC/DC Controller
FEATURES
s s
DESCRIPTIO
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High Efficiency at Full Load Better Cross Regulation Than Nonsynchronous Converters (Multiple Outputs) Soft-Start Minimizes Inrush Current Current Mode Control Provides Excellent Transient Response High Maximum Duty Cycle: 89% Typical 2% Programmable Undervoltage Lockout Threshold 1% Internal Voltage Reference Micropower Start-Up Constant Frequency Operation (Never Audible) 3mm x 4mm 12-Pin DFN Package
The LTC(R)3806 is a current mode synchronous flyback controller that drives N-channel power MOSFETs and requires very few external components. It is intended for medium power applications where multiple outputs are required. Synchronous rectification provides higher efficiency and improved output cross regulation than nonsynchronous converters. The IC contains all the necessary control circuitry including a 250kHz oscillator, precision undervoltage lockout circuit with hysteresis, gate drivers for primary and synchronous switches, current mode control circuitry and soft-start circuitry. Programmable soft-start reduces inrush currents. This makes it easier to design compliant Power Over Ethernet supplies. Low start-up current reduces power dissipation in the start-up resistor and reduces the size of the external startup capacitor. The LTC3806 is available in a 12-pin, exposed pad DFN package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
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48V Telecom Supplies 12V/42V Automotive 24V Industrial VoIP Phone Power Over Ethernet
TYPICAL APPLICATIO
VIN 36V TO 72V R1 51k R2 604k
C7 4.7F LTC3806 RUN SENSE R8 100 ITH FB VIN C1 100F R3 26.7k C2 1nF R4 3.4k INTVCC C3 4.7F SS G2 G1 GND
D1
T1
* * *
M1
M2
C4 0.47F
R5 0.056
R7 12.4k
R6 21k
Figure 1. Multiple Output Flyback Converter for Telecom
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VOUT1 3.3V VOUT2 3A 2.5V 3A M3 C5 470F C6 470F
3806 F01
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LTC3806
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW RUN ITH FB NC VIN INTVCC 1 2 3 13 4 5 6 9 8 7 G1 G2 GND 12 SENSE 11 NC 10 SS
VIN Voltage ............................................................. 25V INTVCC Voltage ......................................................... 8V INTVCC Output Current ........................................ 50mA G1, G2 Voltages ....................... - 0.3V to VINTVCC + 0.3V ITH, FB, SS Voltages .................................- 0.3V to 2.7V RUN Voltage ............................................... - 0.3V to 7V SENSE Pin Voltage ..................................... - 0.3V to 8V Operating Ambient Temperature Range (Note 2) .................................................. - 40C to 85C Junction Temperature (Note 3) ............................ 125C Storage Temperature Range ................. - 65C to 125C
ORDER PART NUMBER LTC3806EDE
DE PART MARKING 3806
DE12 PACKAGE 12-LEAD (4mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 34C/W EXPOSED PAD (PIN 13) IS GND MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VIN(MIN) IQ PARAMETER Minimum Input Voltage Input Voltage Supply Current Quiescent Shutdown Mode Start-Up Mode Rising RUN Input Threshold Voltage Falling RUN Input Threshold Voltage RUN Pin Input Threshold Hysteresis RUN Input Current Feedback Voltage Feedback Pin Input Current Line Regulation Load Regulation Error Amplifier Transconductance SENSE Pin Current (G1 High) SENSE Pin Current (G1 Low) SS Pin Source Current Oscillator Frequency Maximum Duty Cycle Main Control Loop
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VIN = 10V, VRUN = 1.5V, unless otherwise specified.
CONDITIONS (Note 4) (Note 5) VRUN = 0V VRUN > 1.255V, VIN < 7V VIN = 20V
q
MIN 10
TYP
MAX
UNITS V
1000 50 80 1.205 1.181 1.116 1.093 45 1.218 1.212 1.230 1.139 91 1 1.230 18 0.01
q
90 140 1.255 1.279 1.162 1.185 137 60 1.242 1.248 100
VRUN+ VRUN- VRUN(HYST) IRUN VFB IFB VFB/VIN VFB/VITH gm ISENSE(ON) ISENSE(OFF) ISS Oscillator fOSC DC(MAX)
VIN = 20V
q
VIN = 20V VITH = 0.75V (Note 6)
q
VITH = 0.75V (Note 6) 10V VIN 20V VTH = 0.55V to 0.95V (Note 6) ITH Pin Load = 5A (Note 6) 110 VSENSE = 0V VSENSE = 1V VSS = 1.5V 3 210 84 -1
-0.1 650 150 35 0.1 5 250 89 190 50 5 8 290 94
Mho mV A A A kHz %
VSENSE(MAX) Maximum Current Sense Input Threshold
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A A A V V V V mV nA V V nA %/V %
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LTC3806
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VIN = 10V, VRUN = 1.5V, unless otherwise specified.
SYMBOL Regulator VINTVCC INTVCC VIN VLDO(LOAD) VUVL+ VUVL- Gate Drivers tr1 tf1 tr2 tf2 tDEAD Gate Driver 1 Output Rise Time Gate Driver 1 Output Fall Time Gate Driver 2 Output Rise Time Gate Driver 2 Output Fall Time Gate Driver Dead Time CL1 = 3300pF CL1 = 3300pF CL2 = 4700pF CL2 = 4700pF CL1 = 3300pF, CL2 = 4700pF 25 18 25 18 100 100 100 100 100 ns ns ns ns ns INTVCC Regulator Output Voltage INTVCC Regulator Line Regulation INTVCC Load Regulation Rising VIN Threshold Voltage Falling VIN Threshold Voltage VIN = 10V 10V VIN 20V 0 IINTVCC 20mA -6 14 7.5 -3 15 8 16 8.5 6 6.9 7.8 100 V mV % V V PARAMETER CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: The LTC3806E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD * 34C/W)
Note 4: The minimum operating voltage is allowed once operation begins. To begin operation, VIN must be above the rising undervoltage lockout threshold with VRUN above the rising RUN input threshold. Note 5: The dynamic input supply current is higher due to power MOSFET gate charging (QG * fOSC). See Applications Information. Note 6: The LTC3806 is tested in a feedback loop which servos VFB to the reference voltage with the ITH pin forced to a voltage between 0V and 1.4V (the no load to full load operating voltage range for the ITH pin is 0.3V to 1.23V).
TYPICAL PERFOR A CE CHARACTERISTICS
FB Voltage vs Temperature
1.2400 1.2310
1.2350
FB PIN CURRENT (nA)
FB VOLTAGE (V)
1.2300
FB VOLTAGE (V)
1.2250
1.2200
1.2150 -40
-15
35 10 TEMPERATURE (C)
UW
60
FB Voltage Line Regulation
30
TA = 25C
FB Pin Current vs Temperature
25
1.2305
20 15 10 5
1.2300
1.2295
1.2290 85
3806 G01
10 11 12 13 14 15 16 17 18 19 20 VIN (V)
3806 G02
0 -40
-15
10 35 TEMPERATURE (C)
60
85
3806 G03
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LTC3806 TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Mode IQ vs VIN
80 70
TA = 25C
SOFT-START CURRENT (A)
SHUTDOWN MODE, IQ (A)
SHUTDOWN MODE, IQ (A)
60 50 40 30 20 10 0 0 2 4 6 8 10 12 14 16 18 20 VIN (V)
3806 G04
G1 Rise and Fall Time vs CL
250 TA = 25C 120 100 80
TIME (ns) TIME (ns)
200
RUN THRESHOLDS (V)
150
100
50
0
0
4000
12000 8000 CL (pF)
16000
Frequency vs Temperature
260 155 154
MAX SENSE THRESHOLD (mV)
255
FREQUENCY (kHz)
250
245
240 -40
-15
4
UW
3806 G07
Shutdown Mode IQ vs Temperature
80 75
Soft-Start Current vs Temperature
7.0
6.5
70 65 60 55 50 -40
6.0
5.5
-15
10 35 TEMPERATURE (C)
60
85
3806 G05
5.0 -40
-15
10 35 TEMPERATURE (C)
60
85
3806 G06
G2 Rise and Fall Time vs CL
TA = 25C
1.22
RUN Thresholds vs Temperature
TRIP 1.20 1.18 1.16 1.14 RELEASE 1.12 1.10 -40
60 40 20 0
20000
0
4000
12000 8000 CL (pF)
16000
20000
3806 G08
-15
10 35 TEMPERATURE (C)
60
85
3806 G10
Maximum Sense Threshold vs Temperature
153 152 151 150 149 148 147 146
35 10 TEMPERATURE (C)
60
85
3806 G11
145 -40
-15
35 10 TEMPERATURE (C)
60
85
3806 G12
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LTC3806 TYPICAL PERFOR A CE CHARACTERISTICS
SENSE Pin Current vs Temperature
32.0
7.020 7.015 SENSE PIN CURRENT (A)
INTVCC VOLTAGE (V)
7.010 7.005 7.000 6.995
INTVCC VOLTAGE (V)
31.5
31.0
30.5
6.995 6.990 0 10 20 30 INTVCC LOAD (mA) 40 50
3806 G14
30.0 -40
-15
35 10 TEMPERATURE (C)
INTVCC Dropout Voltage vs Current, Temperature
2.8 2.7
DROPOUT VOLTAGE (V)
2.6 EFFICIENCY (%) 2.5 2.4 2.3 2.2 2.1 2.0 1.9 0 10 30 20 INTVCC LOAD (mA) 40 50
3806 G16
UW
60
3806 G13
INTVCC Load Regulation
TA = 25C 7.020 7.015 7.010 7.005 7.000
INTVCC Line Regulation
6.990
85
10
12
14
16 VIN (V)
18
20
3806 G15
Efficiency vs Output Power
90 FIGURE 8 CIRCUIT
TA = -40C
TA = 0C TA = 25C TA = 55C TA = 85C
85
80
75 10 20 30 40 50 60 70 80 90 100 % OF MAXIMUM OUTPUT POWER
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LTC3806
PI FU CTIO S
RUN (Pin 1): The RUN pin provides the user with an accurate means for sensing the input voltage and programming the start-up threshold for the converter. The falling RUN pin threshold is nominally 1.14V and the comparator has 91mV of hysteresis for noise immunity. When the RUN pin is below this input threshold, the gate drive outputs G1 and G2 are held low. The absolute maximum rating for the voltage on this pin is 7V. ITH (Pin 2): Error Amplifier Compensation Pin. The current comparator input threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.4V. FB (Pin 3): Receives the feedback voltage from the external resistor divider across the main output. Nominal voltage for this pin in regulation is 1.230V. NC (Pins 4, 11): Do Not Connect. VIN (Pin 5): Main Supply Pin. Must be closely decoupled to ground. INTVCC (Pin 6): The Internal 6.9V Regulator Output. The gate drivers and control circuits are powered from this voltage. Decouple this pin locally to the IC ground with a minimum 4.7F low ESR ceramic capacitor. GND (Pins 7, 13): Ground Pins. Exposed pad must be tied to electrical ground. G2 (Pin 8): Secondary-Side Gate Driver Output. This pin drives the gates of all of the synchronous rectifiers. G1 (Pin 9): Primary-Side Gate Driver Output. SS (Pin 10): Soft-Start. A capacitor between this pin and ground sets the rate at which the current comparator input threshold may increase when the IC is initially enabled. Increasing the size of the capacitor slows down the ramp rate and reduces the inrush current. SENSE (Pin 12): Current Sense Input for the Control Loop. Connect this pin to the current sense resistor in the source of the primary side power MOSFET. Internal leading edge blanking is provided.
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LTC3806
BLOCK DIAGRA W
SLOPE COMPENSATION SENSE 12 ITH 2 V-TO-I ILOOP FB 3 EA RLOOP OSC PWM LATCH INTVCC
+
C1
S R CURRENT COMPARATOR
G1 9
Q LOGIC
-
INTVCC
G2 8 SS
GND 7
NC: PINS 4 AND 11
+
1.230V VREF BIAS AND START-UP CONTROL
-
gm SOFT-START RUN COMPARATOR 10 RUN
+
C2
1
-
VIN 5
-
UV2
+
REGULATOR
+ - +
UV1 6.9V INTVCC 6
-
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LTC3806
OPERATIO
Main Control Loop The LTC3806 is a constant frequency, current mode flyback converter controller. A secondary-side gate driver capable of driving several MOSFET synchronous rectifiers is provided. To insure best cross regulation, DC/DC converters using this controller operate in forced continuous conduction (current is always flowing in either the primary or secondary winding(s) of the transformer.) For circuit operation, please refer to the Block Diagram of the IC and Figure 1. In normal operation, the primary-side power MOSFET is turned on when the oscillator sets the PWM latch and is turned off when the current comparator C1 resets the latch. VOUT1 is divided down and compared to an internal 1.230V reference by error amplifier EA, which outputs an error signal at the ITH pin. The voltage of the ITH pin sets the current comparator C1 input threshold. When the load current on either output increases, a fall in the FB voltage relative to the reference voltage causes the ITH pin to rise increasing the primary-side peak current thereby maintaining regulation. Regulation of VOUT2 is indirect, occurring via transformer action. The RUN pin and undervoltage comparators control whether the IC is enabled or is in a low current state. With
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the RUN pin below 1.139V, the chip is off and the input supply current is typically only 50A. If the RUN pin is above 1.230V, most internal circuitry remains off until VIN exceeds the undervoltage comparator UV2 threshold. This reduces start-up current to approximately 80A allowing smaller values for C1 and larger values for R1 to be used. The undervoltage comparator UV1 keeps G1 and G2 low until INTVCC voltage is > 4.7V to insure that gate drivers will switch the external power MOSFETs properly. Prior to normal operation, soft-start pin SS is low clamping the output of the V-to-I converter to a low value causing current comparator C1 to trip at a low threshold. Once operation begins, the SS pin ramps up causing the clamp voltage to rise as well. This allows progressively higher trip points on comparator C1 and progressively higher peak currents to be supplied to the primary of the transformer. Soft-start is completed when the voltage on the SS pin exceeds the voltage on the ITH pin. The nominal operating frequency of the LTC3806 is 250kHz. Since forced continuous operation is used, the noise spectrum over all operating conditions is well controlled with virtually all noise occurring at the operating frequency and its harmonics.
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LTC3806
APPLICATIO S I FOR ATIO
INTVCC Regulator Bypassing and Operation
An internal voltage regulator produces the 6.9V supply that powers the gate drivers and logic circuitry within the LTC3806. The INTVCC regulator can supply up to 50mA and must be bypassed to ground immediately adjacent to the IC pins with a minimum of 4.7F ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate drivers. In an actual application, most of the IC supply current is used to drive the gate capacitances of the power MOSFETs. As a result, high input voltage applications with large power MOSFETs can cause the LTC3806 to exceed its maximum junction temperature rating. The junction temperature can be estimated using the following equations: IQ(TOT) = IQ + f * QG PIC = VIN * (IQ + f * QG) TJ = TA + PIC * RTH(JA) where IQ is the static supply current QG is the total gate charge of all external power MOSFETs PIC is the power dissipated in the IC f is the switching frequency, nominally 250kHz RTH(JA) is the package thermal resistance, junction to ambient, nominally 34C/W for the 12-pin DFN package As an example, consider a 2-output power supply that uses an Si7450DP primary-side power MOSFET, that has a maximum total gate charge of 42nC and two Si4840DY power MOSFETs (one for each output), each of which has 28nC maximum total gate charge. The total gate charge is: QG = 42nC + 2 * 28nC = 98nC The total supply current is: IQ(TOT) = 2000A + 98nC * 250kHz = 27mA This demonstrates how significant the gate charge current can be when compared to static quiescent current in the IC.
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If VIN is set to 10V, the power dissipation is: PIC = 10 * 27mA = 270mW and the junction temperature (assuming 70 degree ambient temperature) is: TJ = 70C + 270mW * 120C/W = 102.4C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked when operating at high VIN. If junction temperature is too high, using a separate transformer winding to lower VIN may be tried. Prior to adding an additional transformer winding (which raises transformer cost), be sure to check with power MOSFET manufacturers for their newest low QG, low RDS(ON) devices. Power MOSFET manufacturing technologies are continually improving, with newer and better performance devices being introduced almost yearly. Output Voltage Programming This IC will generally be used in DC/DC converters with multiple outputs. The output voltage of the master output (VOUT1) is set by a resistor divider according to the following formula: R6 VOUT1 = 1.230 V * 1 + R7 The external resistor divider is connected as shown in Figure 1. The resistors R6 and R7 are typically chosen so that the error caused by the current flowing into the FB pin during normal operation is less than 1% (this translates to a maximum value of R7 of about 120k). The nominal slave output (VOUT2) voltage is set according to the following formula: VOUT2 = VOUT1 * N21 where N21 is the turns ratio of the transformer windings between VOUT2 and VOUT1. If additional slave outputs are added their voltage is determined by the equation: VOUTN = VOUT1 * NN1 where NN1 is the turns ratio of the transformer windings between VOUTN and VOUT1.
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LTC3806
APPLICATIO S I FOR ATIO
Cross regulation and tracking between the master and slave outputs are impacted by transformer and secondary-side power MOSFET selection. Select a power MOSFET with low on resistance. In addition, a transformer with low winding resistances and highest coupling coefficient will have better cross regulation and tracking. Composite Feedback In applications where accuracy is important on more than one output, composite feedback may be used. This sacrifices some of the accuracy of one output for improved accuracy on the other output(s). Figure 2 shows how composite feedback can be applied to two outputs.
OUT1 OUT2
R6A
R6B FB R7
3806 F02
Figure 2. Composite Feedback
+
R2 RUN VIN
INPUT SUPPLY
OPTIONAL FILTER CAPACITOR
R1 1.230V REFERENCE
-
Figure 3a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin
+
RUN COMPARATOR RUN 6V EXTERNAL LOGIC CONTROL 1.230V
+ -
3806 F03b
Figure 3b. On/Off Control Using External Logic
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Select a value for R7 less than or equal to 120k. Now choose the fraction K of the total feedback taken from VOUT1. The higher the fraction used, the tighter VOUT1 is controlled, but the poorer VOUT2 is controlled (since it contributes less to the total feedback). The values for R6A and R6B can now be calculated:
R6 A = R6B = R7 VOUT1 - 1 K VREF R7 VOUT2 - 1 1 - K VREF
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This technique can easily be extended to more outputs if needed. Programming Turn-On and Turn-Off Thresholds with the RUN Pin The LTC3806 leaves a comparator detection circuit and the voltage reference active even when the device is shut down (Figure 3). This allows users to accurately program an input voltage at which the converter will turn on and off.
+
6V
RUN COMPARATOR BIAS AND START-UP CONTROL
-
GND
3806 F03a
VIN R2 1M RUN COMPARATOR
RUN 6V
INPUT SUPPLY
+ -
-
GND 1.230V
3806 F03c
Figure 3c. External Pull-Up Resistor On RUN Pin for "Always On" Operation
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LTC3806
APPLICATIO S I FOR ATIO
The rising threshold voltage on the RUN pin is equal to the internal reference voltage of 1.230V. The comparator has 91mV of hysteresis to increase noise immunity. The turn-on and turn-off input voltage thresholds are programmed using a resistor divider according to the following formulas:
R2 VIN(OFF) = 1.139 V * 1 + R1 R2 VIN(ON) = 1.230 V * 1 + R1
The resistor R1 is typically chosen to be less than 1M. For applications where the RUN pin is only to be used as a logic input, the user should be aware of the 7V Absolute Maximum Rating for this pin! The RUN pin can be connected to the input voltage through an external 1M resistor, as shown in Figure 3c, for "always on" operation. Application Circuits A basic LTC3806 application circuit is shown in Figure 1. External component selection is driven by the characteristics of the load and the input supply. Duty Cycle Considerations Current and voltage stress on the power switch and synchronous rectifiers, input and output capacitor RMS currents and transformer utilization (size vs power) are impacted by duty factor. Unfortunately duty factor cannot be adjusted to simultaneously optimize all of these requirements. In general, avoid extreme duty factors since this severely impacts the current stress on most of the components. A reasonable target for duty factor is 50% at nominal input voltage. Using this rule of thumb, calculate the ideal transformer turns ratio: NIDEAL = VOUT1 1 - D * VIN D
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For a 50% duty factor, this reduces to:
NIDEAL = VOUT1 VIN
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If NIDEAL is integer, use this for your turns ratio. If not, find a ratio of small integers that comes close to NIDEAL. If these conditions are met, bifilar winding techniques can be used that will improve coupling coefficient. Cross regulation will be better and primary-side snubbing may be reduced or eliminated. The selected turns ratio doesn't have to be perfectly equal to NIDEAL because a flyback converter's output voltage is not set through transformer action. Instead, the transformer stores energy when the primary-side switch turns on and transfers this energy to the output(s) by flyback action when the primary-side switch turns off. Cross regulation may be improved by using a target duty factor which is less than 50%. This improves cross regulation because the secondary-side MOSFETs (synchronous rectifiers) will be on a larger percentage of the time (thereby increasing the average coupling between the outputs). Duty factor is reduced by proportionately increasing all turns ratios. Reduced duty factor has the following effect on MOSFET stresses:
LOCATION Primary Secondary MOSFET CURRENT STRESS Increased Reduced MOSFET VOLTAGE STRESS Reduced Increased
The duty factor with the selected turns ratio will equal:
D= VOUT1 VOUT1 + (N * VIN)
While the output(s)/input turns ratio are not critical, the turns ratio between outputs are critical and affect the accuracy of the slave output voltages.
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LTC3806
APPLICATIO S I FOR ATIO
Some common secondary turns ratios:
VOUT 2.5 3.3 3.3 5.0 1.8 3.3 1.8 2.5 2.5 3.3 5.0 TURNS 3 4 2 3 6 11 5 7 3 4 6
For example, assume we need a regulator that operates with a nominal 48V input to produce one 3.3V output and one 5V output. The ideal turns ratio for the 3.3V (master) output is: 3.3 = 0.06875 48 We select a turns ratio of 1/15 or N1 = 0.066... NIDEAL1 = For the 5V output, the ideal turns ratio is: NIDEAL2 = N1 * If we choose: 1 10 and we assume OUT1 is exact, the voltage on slave output 2 is: N2 =
1 VOUT2 = 3.3 * 10 = 3.3 * 1.5 = 4.95V 1 15
5 = 0.1010... 3.3
This does not include any other errors, so make sure that the error in VOUT2 is only a fraction of what your specification allows. When dealing with large numbers of outputs trial and error is usually required to get reasonable turns ratios on all outputs while keeping the errors (due to imperfect turns ratios) low. For the selected turns ratios, the duty factor for this design with 48V input would be:
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D= VOUT1 = VOUT1 + (N * VIN ) 3.3V = 0.508 48 V 3.3V + 15 Input Power The maximum input power is:
PIN = N=1POUTK K Eff
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where POUTK is the maximum power supplied by output K and Eff represents the efficiency of the converter. Continuing the previous example, assume OUT1 delivers 3.3V at 2A and OUT2 delivers 4.95V at 0.5A. For a conversion efficiency at maximum output power of 80%: PIN = 3.3V * 2A + 4.95V * 0.5A = 11.34W 0.80
Transformer Selection The transformer primary inductance, LP, is selected based on the percentage peak-to-peak ripple current (X) in the transformer relative to its maximum value. In general, X should range from 20% to 40% ripple current (i.e., X = 0.2 to 0.4). Higher values of ripple will increase conduction losses, while lower values will require larger cores. Ripple current and percentage ripple will be largest at minimum duty factor D, in other words at the highest input voltage. LP can be calculated from:
LP =
VIN(MAX)2 * DMIN2 f * XMAX * PIN
where f is nominally 250kHz. Continuing the example, allow 40% maximum ripple at a maximum input voltage of 72V: 3.3V = 0.407 72V 3.3V + 15 2 * 0.4072 72V LP = = 757H 250000Hz * 0.4 * 11.34W DMIN =
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LTC3806
APPLICATIO S I FOR ATIO
3.3V = 0.579 36 V 3.3V + 15
For a minimum input voltage of 36V, the largest duty factor is: DMAX =
and the minimum percentage ripple is: VIN2 * DMAX2 XMIN = f * LP * PIN = 36 V2 * 0.5792 250kHz * 757H * 11.34W = 20.2%
MAXIMUM CURRENT SENSE VOLTAGE (mV)
Transformer Core Selection Once LP is known, the type of transformer must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite cores. Actual core loss is independent of core size for a fixed inductance, but is very dependent on the inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Generally, there is a tradeoff between core losses and copper losses that needs to be balanced. In addition, increased winding resistance will degrade cross regulation. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper losses and preventing saturation. Ferrite core material saturates "hard," meaning that the inductance collapses rapidly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequently, output voltage ripple. Do not allow the core to saturate! The maximum peak primary current occurs at minimum VIN:
IPK
PIN X = * 1 + MIN VIN(MIN) * DMAX 2
Current Sense Resistor Selection The control circuit limits the maximum voltage drop across the sense resistor to about 120mV (at low duty
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cycle), and only about 70mV at a duty cycle of 92% due to slope compensation. Use Figure 4 and DMAX to determine the maximum allowable drop in the sense resistor. Using this value calculate:
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RSENSE
200
VDROP IPK
TA = 25C
150
100
50
0
0
0.2
0.5 0.4 DUTY CYCLE
0.8
1.0
3806 F04
Figure 4. Maximum SENSE Threshold Voltage vs Duty Cycle
Capacitor Selection In a flyback converter, the input and output current flows in pulses placing severe demands on the input and output filter capacitors. The input and output filter capacitors should be selected based on RMS current ratings and ripple voltage. Select an input capacitor with a ripple current rating greater than: IRMS = PIN VIN(MIN) 1 - DMAX DMAX
Continuing the example: IRMS = 11.34W 1 - 0.579 = 0.269 ARMS 36 V 0.579
Low effective series resistance and inductance is also important in the input capacitor since it affects the electromagnetic interference suppression. In some instances high ESR can also produce stability problems because flyback converters exhibit a negative input resistance
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LTC3806
APPLICATIO S I FOR ATIO
characteristic. Refer to Application Note 19 for more information. The output capacitor is sized to handle the ripple current and to insure acceptable output voltage ripple. The output capacitor should have a ripple current rating greater than:
IRMS = IOUT
DMAX 1- DMAX
This should be calculated for each output. For our example, the OUT1 capacitor needs an RMS current rating greater than: IRMS = 2A 0.579 = 2.35ARMS 1 - 0.579
The OUT2 capacitor RMS current rating is calculated in a similar manner. The capacitor rating should be greater than 586mARMS. One final note, most capacitor manufacturers base their ripple current ratings on only 2000 hours life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Contributions of ESR (equivalent series resistance), ESL (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct component for a given output ripple voltage. The effects of these three parameters (ESR, ESL and bulk C) on the output voltage ripple waveform are illustrated in Figure 5 for a typical flyback converter.
PRIMARY CURRENT
SECONDARY CURRENT
OUTPUT VOLTAGE RIPPLE WAVEFORM
Figure 5. Typical Flyback Converter Waveforms (Single Output)
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The capacitance calculation begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the ESR step and the charging/discharging V. For the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the ESR step and the charging/discharging V. This percentage ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor can be determined using the following equation:
ESRCOUT 0.01 * VOUT * (1 - DMAX ) IOUT
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For the bulk C component, which also contributes 1% to the total ripple:
COUT
IOUT 0.01 * VOUT * F
For many designs it is possible to choose a single capacitor type that satisfies both the ESR and bulk C requirements for the design. In certain demanding applications, however, the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. For example, using a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic capacitor can be used to supply the required bulk C.
IPRI
IPRI N VCOUT
VESR
RINGING DUE TO ESL
3806 F05
LTC3806
APPLICATIO S I FOR ATIO
Continuing our previous example the filter capacitor for output 1 needs:
ESRCOUT 0.01 * 3.3V * (1 - 0.579) = 7m 2A 2A COUT = 242F 0.01 * 3.3V * 250kHz
To get an electrolytic capcitor with an ESR this low would require COUT much larger than 242F. Combining a low ESR ceramic capacitor in parallel with an electrolytic capacitor provides better filtering at lower cost. For output 2, the output capacitor needs an ESR less than 42m and a bulk C greater than 40.4F. This can be achieved with a single high performance capacitor such as a Sanyo OS-CON or equivalent. Once the output capacitor ESR and bulk capacitance have been determined, the overall ripple voltage waveform should be verified on a dedicated PC board. Parasitic inductance from poor layout can have a significant impact on ripple. Refer to the layout section for details. Power MOSFET Selection Important selection criteria for the power MOSFETs include the "on" resistance RDS(ON), input capacitance, drain-to-source breakdown voltage (BVDSS) and maximum drain current (ID(MAX)). Narrow the choices for power MOSFETs by first looking at the maximum drain currents. For the primary-side power MOSFET:
IPK =
PIN X * 1 + MIN VIN(MIN) * DMAX 2
For each secondary-side power MOSFET: IPK = IOUT 1 - DMAX X * 1 + MIN 2
From the remaining MOSFET choices, narrow the field based on BVDSS. Select a primary-side power MOSFET with a BVDSS greater than:
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BVDSS IPK VOUT(MAX) LLKG + VIN(MAX) + CP N
where LLKG is the primary-side leakage inductance and CP is the primary-side capacitance (mostly from the COSS of the primary-side power MOSFET). A snubber may be added to reduce the leakage inductance related spike. For more information on snubber design, refer to Application Note 19. For each secondary-side power MOSFET, the BVDSS should be greater than: BVDSS VOUT + VIN(MAX) * N Next, select a logic-level MOSFET with acceptable RDS(ON) at the nominal gate drive voltage (usually 6.9V--set by the INTVCC regulator). Calculate the required RMS currents next. For the primaryside power MOSFET:
IRMSPRI = PIN VIN(MIN) * DMAX
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For each secondary-side power MOSFET:
IRMSSEC =
IOUT 1 - DMAX
Calculate MOSFET power dissipation next. Because the primary-side power MOSFET operates at high VDS, a term for transition power loss must be included in order to get an accurate fix on power dissipation. CMILLER is the most critical parameter in determining the transition loss but is not directly specified on MOSFET data sheets. CMILLER can be calculated from the gate charge curve included on most data sheets (Figure 6). The curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. The initial slope is the result of the gate-to-source and the gate-to-drain capacitance. The flat portion of the curve is the result of the Miller (gate-to-drain) capacitance as the drain voltage drops. The upper sloping line is due to the gate-to-drain accumulation capacitance and the gate-to-source capacitance. The Miller
3806f
15
LTC3806
APPLICATIO S I FOR ATIO
MILLER EFFECT VGS a b
QIN CMILLER = (QB - QA)/VDS
+
VGS
-
IGATE
3806 F06
Figure 6. Gate Charge Curve and Test Circuit
charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given VDS, but can be adjusted for different VDS voltages by multiplying by the ratio of the application VDS to the curve specified VDS values. To estimate the CMILLER term, take the change in gate charge from points a and b on the manufacturers data sheet and divide by the specified VDS. With CMILLER determined, calculate the primary-side power MOSFET power dissipation: PDPRI = IRMSPRI2 * RDS(ON) (1 + ) + VIN(MAX) PIN(MAX) 1 * * RDR * CMILLER * *f VINTVCC - VTH DMIN where RDR is the GATE1 driver resistance (maximum is approximately 6), VTH is the typical gate threshold voltage for the specified power MOSFET and f is the operating frequency, typically 250kHz. The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but = 0.005/C can be used as an approximation for low voltage MOSFETs. The secondary-side power MOSFETs typically operate at substantially lower VDS, so transition losses can be neglected. The dissipation may be calculated using: PDSEC = IRMSSEC2 * RDS(ON) (1 + ) For a known power dissipation in the power MOSFETs, the junction temperatures can be obtained from the equation: TJ = TA + PD * RTH(JA) where TA is the ambient temperature and RTH(JA) is the MOSFET thermal resistance from junction to ambient.
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VIN VDS
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Compare TJ against your initial estimate for TJ and if necessary, recompute , power dissipations and TJ. Iterate as necessary. Selecting the Compensation Network Load step testing can be used to empirically determine compensation. Application Note 25 provides information on the technique. When the regulator has multiple outputs, compensation should be optimized for the master output. PC Board Layout Checklist 1. In order to minimize switching noise and improve output load regulation, the GND pin of the LTC3806 should be connected directly to 1) the negative terminal of the INTVCC decoupling capacitor, 2) the negative terminal of the output decoupling capacitors, 3) the bottom terminal of the current sense resistor, 4) the negative terminal of the input capacitor and 5) at least one via to the ground plane immediately adjacent to Pin 6 (GND). 2. Beware of ground loops in multiple layer PC boards. Try to maintain one central ground node on the board and use the input capacitor to avoid excess input ripple for high output current power supplies. If the ground plane is to be used for high DC currents, choose a path away from the small-signal components. 3. Place the CVCC capacitor immediately adjacent to the INTVCC and GND pins on the IC package. This capacitor carries high di/dt MOSFET gate drive currents. A low ESR X5R 4.7F ceramic capacitor works well here. 4. The high di/dt loop from the bottom terminal of the input capacitor through the sense resistor, primaryside power MOSFET, transformer primary and back through the input capacitor should be kept as tight as possible in order to reduce EMI. Also keep the loops formed by the outputs as tight as possible. 5. Check the switching waveforms of the MOSFETs using the actual PC board layout. Measure directly across the power MOSFET terminals to verify that the BVDSS specification of the MOSFET is not exceeded due to inductive ringing. If this ringing cannot be avoided and
3806f
DEVICE UNDER TEST
LTC3806
APPLICATIO S I FOR ATIO
exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalanche-rated power MOSFET. 6. Place the small-signal components away from high frequency switching nodes. (All of the small-signal components on one side of the IC and all of the power components on the other.) This allows the use of a pseudo-Kelvin connection for the signal ground, where high di/dt gate driver currents flow out of the IC ground pin in one direction (to the bottom plate of the INTVCC decoupling capacitor) and small-signal currents flow in the other direction. 7. Minimize the capacitance between the SENSE pin trace and any high frequency switching nodes. The LTC3806 contains an internal leading edge blanking time of approximately 180ns, which should be adequate for most applications.
R1 22 VIN 25V TO 60V
D1 1N4148
C5 2.2F
R5 232k
R4 47k 5 3 Q4 Si4490DY Q1 Si7806DN
1 2 C16 R9 100pF 33k C14 1nF R10 12.4k 3 4 5 6 C18 100F C19 220nF D4 20V
LTC3806 12 RUN SENSE 11 C15 220nF ITH NC 10 SS FB 9 G1 NC 8 G2 VIN 7 INTVCC GND C20 4.7F R16 R13 76.8k 42.3k
R17 12.4k
Figure 7. Synchronous Flyback
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8. For optimum load regulation and true remote sensing, the top of the output resistor divider should connect independently to the top of the the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resistors near the LTC3806 in order to keep the high impedance FB node short. 9. For applications with multiple switching power converters which connect to the same input supply, make sure that the input filter capacitor for the LTC3806 is not shared with other converters. AC input current from another converter could cause substantial input voltage ripple and this could interfere with the operation of the LTC3806. A few inches of PC trace or wire (L 100nH) between the CIN of the LTC3806 and the actual source VIN should be sufficient to prevent current sharing problems.
T1 XFMR_EFD20 7 R3 TBD C7 220pF 12 11 6 10 1 2 8 9 4 3.3V 2A C8 470F POSCAP 5V 1.5A C6 100F D2 R2 C1 B260A 10 1nF 12V 400mA C2 10F
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+
Q5 Si7806DN Q2 Si7806DN
R14 0.056
R18 100k C25 100nF D8 10V -5V C26 1.5A 100F
3806 F07
17
LTC3806
APPLICATIO S I FOR ATIO
Table 1. Recommended Component Manufacturers
VENDOR AVX BH Electronics Coiltronics Diodes, Inc. Fairchild General Semiconductor International Rectifier IRC Kemet Magnetics Inc. Microsemi Murata-Erie Nichicon On Semiconductor Panasonic Sanyo Taiyo Yuden TDK Thermalloy Tokin United Chemicon Vishay/Dale Vishay/Siliconix Vishay/Sprague Zetex COMPONENTS Capacitors Transformers Transformers Diodes MOSFETs Diodes MOSFETs, Diodes Sense Resistors
Tantalum Capacitors Toroid Cores Diodes Capacitors Capacitors Diodes Capacitors Capacitors Capacitors Capacitors, Transformers Heat Sinks Capacitors Capacitors Resistors MOSFETs Capacitors Small-Signal Discretes
TYPICAL APPLICATIO
VIN 36V TO 72V R5 330k
Synchronous Forward Application
T1 PULSE PA0031 C1 1.5F C4 330pF R1 220 L1 4.7H
R6 51k
R11 D1 100 1N4148
R7 12.5k D2 20V
R9 3.3k C7 1nF C5 100F C6 100pF
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TELEPHONE 207-282-5111 952-894-9590 407-241-7876 805-446-4800 408-822-2126 516-847-3000 310-322-3331 361-992-7900 408-986-0424 800-245-3984 617-926-0404 770-436-1300 847-843-7500 602-244-6600 714-373-7334 619-661-6835 408-573-4150 562-596-1212 972-243-4321 408-432-8020 847-696-2000 605-665-9301 800-554-5565 207-324-4140 631-543-7100 WEB ADDRESS avxcorp.com bhelectronics.com coiltronics.com diodes.com fairchildsemi.com gerneralsemiconductor.com irf.com irctt.com kemet.com mag-inc.com microsemi.com murata.co.jp nichicon.com onsemi.com panasonic.com sanyo.co.jp t-yuden.com component.tdk.com aavidthermalloy.com tokin.com chemi-com.com vishay.com vishay.com vishay.com zetex.com
* *
VOUT 3.3V 8A 1 2 3 4 5 6 LTC3806 NC RUN ITH FB VIN INTVCC C3 4.7F R10 12.5k R8 20.5k
3806 TA01
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NC SENSE SS G2 G1 GND
12 11 10 9 8 7 C8 470nF R2 0.1 Q2 Si7358DP Q1 Si7450DP Q3 Si7448DP C2 330F
3806f
LTC3806
PACKAGE DESCRIPTIO
3.50 0.05 1.70 0.05 2.20 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 3.30 0.05 (2 SIDES) 0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 0.10 (2 SIDES) R = 0.20 TYP 3.00 0.10 (2 SIDES) 1.70 0.10 (2 SIDES) PIN 1 NOTCH
(UE12/DE12) DFN 0603
PIN 1 TOP MARK (NOTE 6)
0.200 REF
BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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UE/DE Package 12-Lead Plastic DFN (4mm x 3mm)
(Reference LTC DWG # 05-08-1695)
0.65 0.05 7 R = 0.115 TYP 0.38 0.10 12 0.75 0.05 6 0.25 0.05 3.30 0.10 (2 SIDES) 1 0.50 BSC 0.00 - 0.05
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19
LTC3806
TYPICAL APPLICATIO
VIN 25V TO 60V L1 3.3H C1 10F 63V ELEC C2 220nF 1206
+
GND R1 232k 0805 R2 47k 0805 1 2
R3 12.4k 0603
R4 C9 33k 100pF C8 0603 0603 1nF 0603
D3 20V 225mW
+
C13 100F 35V TANT 7343
RELATED PARTS
PART NUMBER LT 1619 LTC1624 LTC1700 LT1725 LTC1871 LTC1872 LT1910 LT1930 LT1931 LT1950 LTC3401/LTC3402 LT3781/LTC1698 LTC3803
(R)
DESCRIPTION Current Mode PWM Controller Current Mode DC/DC Controller No RSENSETM Synchronous Step-Up Controller General Purpose Isolated Flyback Controller Wide Input Range Current Mode No RSENSE Controller SOT-23 Boost Controller Protected High Side MOSFET Driver 1.2MHz SOT-23 Boost Converter Inverting 1.2MHz, SOT-23 Converter Single Switch Forward Controller 1A/2A, 3MHz Synchronous Boost Converters 36V to 72V Input Isolated DC/DC Converter Chipset SOT-23 Flyback Contoller
No RSENSE is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
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D1 1N4148W SOD123 C3 2.2F 100V 1812 T1 XFMR EFD20 12 11 7 6 10 8 9 4 5 3 C5 47F 1812 D2 1A 60V B260A SMA C4 10F 1812 VOUT 12V 400mA GND VOUT 5V 400mA
+
C6 470F 4V POSCAP 7343
C7 100F 1210
VOUT 3.3V 3A
GND Q1 Si4490 LTC3806 1 12 C12 RUN SENSE 2 11 220nF 0603 NC ITH 3 10 FB SS 4 9 NC G2 5 8 VIN G1 6 7 INTVCC GND GND C15 4.7F 10V 0805 R6 12.4k 0603 13 R7 20.5k 0603
3806 F08
R5 0.033 1206 Q2 Si7806DN Q3 Si7806DN Q4 Si7806DN
+
C10 470F 4V POSCAP 7343
C11 100F 1210
VOUT 2.5V 2A
C14 220nF 0603
FB
Figure 8. Mulitple Output Flyback Converter for Telecom
COMMENTS 300kHz Fixed Frequency, Boost, SEPIC Flyback Topology SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design; VIN Up to 36V Up to 95% Efficiency, Operation as Low as 0.9V Input Drives External Power MOSFET, Senses Output Voltage Directly from Primary Side Switching--No Optoisolator Required, 16-Pin SSOP 50kHz to 1000kHz Frequency; Boost, Flyback and SEPIC Topology Delivers Up to 5A, 550kHz Fixed Frequency, Current Mode 8V to 48V Power Supply Range; Protected from -15V to 60V Supply Transients, Short-Circuit Protection, Automatic Restart Timer Up to 34V Output, 2.6V VIN 16V, Miniature Design Positive-to-Negative DC/DC Conversion, Miniature Design 3V VIN 25V, 25W to 500W, Programmable Slope Compensation Up to 97% Efficiency, Very Small Solution, 0.5V VIN 5V Synchronous Operation; Overvoltage/Undervoltage Protection; 10W to 100W Power Supply; 1/2-, 1/4-Brick Footprint Adjustable Slope Compensation, Internal Soft-Start, 200kHz
LT/TP 0104 1K * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2004

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